Wafer-Level Packaging; WLP

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Wafer-Level Packaging

Wafer-Level Packaging (WLP) refers to the technology of packaging an integrated circuit at wafer level, instead of the traditional process of assembling the package of each individual unit after wafer dicing. WLP is essentially a true chip-scale packaging (CSP) technology, since the resulting package is practically of the same size as the die. Furthermore, wafer-level packaging paves the way for true integration of wafer fab, packaging, test, and burn-in at wafer level, for the ultimate streamlining of the manufacturing process undergone by a device from silicon start to customer shipment.

Wafer-level packaging basically consists of extending the wafer fab processes to include device interconnection and device protection processes. However, there is no single industry-standard method of doing this at present. In fact, according to an article in www.future-fab.com, there are at least four major WLP technology classifications in existence today, based on a study by Prismark and TechSearch International.

The four (4) WLP technology classifications according to Prismark and TechSearch International* are the:

1) Redistribution Layer and Bump technology, which is used by: Amkor (Ultra CSP™), Apack, Aptos, ASE (Ultra CSP™), ASAT Chipbond, Dallas Semi (2 lead), FCT (Ultra CSP™), Fraunhofer Institute, FuPo, Hitachi, Hyundai, National Semi (µSMD™), PacTech, Sandia Labs, Seiko Epson, SPIL (Ultra CSP™), Unitive (ExtremeCSP™) ;

2) Encapsulated Copper Post technology, which is used by: Casio, Fujitsu (SuperCSP™), IEP, Oki Electric, TI, Shinko (SuperCSP™ license), Toshiba;

3) Encapsulated Wire Bond technology, which is used by: Form Factor (Wow™, MOST™), Shinko, Hyundai, Infineon (Wow‰ licensees); and

4) Encapsulated Beam Lead technology, which is used by: ChipScale (Intarsia, M-Pulse Microwave), ShellCase (ShellBGA™), Tessera (WAVE™).

*source: www.future-fab.com

Redistribution Layer and Bump technology, the most widely-used WLP technology, extends the conventional wafer fab process with an additional step that deposits a multi-layer thin-film metal rerouting and interconnection system to each device on the wafer. This is achieved using the same standard photolithography and thin film deposition techniques employed in the device fabrication itself.

This additional level of interconnection redistributes the peripheral bonding pads of each chip to an area array of underbump metal (UBM) pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these UBM pads.

Aside from providing the WLP's means of external connection, this redistribution technique also improves chip reliability by allowing the use of larger and more robust balls for interconnection and better thermal management of the device's I/O system.

Figure 1. Photos of two wafer-level packaged devices from

Dallas/Maxim; source:www.maxim-ic.com

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See also: Wafer-level Test/Burn-in

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