Chip Scale Package - CSP

Assembly Links:

Wafer Backgrind

Die Preparation

Die Attach

Wirebonding

Molding

See Also:

Wafer-level Packaging

Flip Chip Assembly

BGA

Semicon Manufacturing

Assembly Equipment

Chip Scale Package (CSP) - Page 2 of 2

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A typical chip scale packaging process starts with the mounting of the die on the interposer using epoxy, usually of non-conductive type (although conductive epoxy is also used when the die backside needs to be connected to the circuit). The die is then wirebonded to the interposer using gold or aluminum wires. Wirebond profiles must be as low and as close to the die as possible in order to minimize package size.

Plastic encapsulation to protect the die and wires then follows, usually by transfer molding. After encapsulation, solder balls are attached to the bottom side of the interposer, after which the package is marked. Finally, the parts are singulated from the leadframe.

Figure 3. Cross-section of a Wirebonded CSP

Figure 4. Cross-section of a Flip-chip CSP

The chip scale package is relatively new, so industry standards for producing CSP's have not yet been completely developed. Nonetheless, the Institute for Interconnecting and Packaging Electronic Circuits (IPC) has already released J-STD-012, "Implementation of Flip Chip and Chip Scale Technology." This document discusses technology overview and design considerations, as well as material, processing, mounting, interconnection, reliability, and standardization aspects of CSP manufacturing.

The industry is moving towards the development of more chip scale packaging standards. Some of the new standards being developed as of this writing are, in fact, defined by J-STD-012. These standards are shown in Table 1.

Table 1. Flip Chip and CSP Standards Currently Undergoing Development

Std No. 102	Mechanical outline Standard for Flip Chip or Chip Scale Configurations
Std No. 103	Performance Standard for Flip Chip/Chip Scale Bumps
Std No. 104	Test Methods for Flip Chip or Chip Scale Performance
Std No. 105	Flip Chip/Chip Scale Carrier Tray Standard
Std No. 106	Bare Dice as Flip Chip or Chip Scale Configuration Management Standard
Std No. 107	Design Standard for Flip Chip and Chip Scale Mounting Structures
Std No. 111	Design Standard for Flip Chip/Chip Scale Assembly Configuration
Std No. 112	Standard for Flip Chip/Chip Scale Assembly Performance Requirements
Std No. 113	Test Methods for Qualification and Evaluation of Flip Chip/Chip Scale Assemblies
Std No. 114	Standard for Flip Chip/Chip Scale Assembly Rework and Repair Techniques
Std No. 115	Flip Chip/Chip Scale Assembly Reliability Standard
Std No. 120	Qualification and Performance Standard for Flux used in Flip Chip Assembly

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