Does anyone knows how to perform FA on PLL circuit?

Guest

Hello,

I'm working in a FA lab and I'm in front of a big problem: I have to do a failure analysis on a PLL circuit. I don't how to do because:
1. I don't really know what kind of equipement I need (especially what kind of probe needle).
2. As a PLL is a loop circuit, if it's failing, I suspect that every node i will check will be bad. So I don't really know how to determine where is the defect...

Does anyone has some experience in analyzing such a circuit? What advice could you give to me? Have you got some tricks?

Thank you very much for you help.

Simon

"Knowledge is the only thing that increases when you share it." Wink

Joined: 08 Jun 2026 Posts: 18 Location: CV

Hi Simon,

First you should ask your test (ATE or product) guy the findings on your tester / ATE setup. Has he/she zeroed in on which specific parameter causes the PLL chip to fail? Are the reference clock and the feedback clock 'locking'? Are the input voltage levels driven (sometimes "low" input drive voltages cause a noisy output freq) such that the correct output frequency (or frequencies) are met? Try to debug this first with your test guy on your ATE platform so you can identify which input stimulus is causing the failures and also, you can focus on a certain area on your bench setup. You can also use the schematic diagram (normally found in product datasheets) of your IC to aid you on your bench setup.

Polgi-Wan

Posted: Thu Jul 28, 2026 12:09 am Post subject:

Hello Polgi-Wan,

Thank you for your response. Apparently, you seem to have some experience on this kind of circuit. Maybe I can detail my problem: the die I have to analyze is a 400MHz frequency generator. It is made with a PLL and a internal oscillator. The failure I have is a bad 400MHz signal (the spectrum is not good, I have a lot of noise): this is the only data I have. I have also an access to the complete schematic of the die.
To do this analysis, I have to probe RF signals within the die. So here are my questions:
- What model of probe needle would you use ? (in order not to disturb the die and to measure correct RF signals)
- How would you proceed to determine the defect localization as everything is looped and everything is working wrong...

I hope I don't ask too many questions Wink

Thanks.

Joined: 20 Jun 2026 Posts: 76

Simon,

I've used PLL's in projects before but I have not yet done FA on them, so I apologize if the inputs I'll be giving below are not applicable to your device.

You need to also get a die circuit schematic diagram that corresponds to your die lay-out plot. With it you might be able to identify the major nodes that connect the various stages of the PLL, including the feedback loops.

Try isolating the various stages and feedback loops of the circuit by cutting these nodes (through laser cutting or with the probe needles). Do this on a good device also. You can then compare the output characteristics of each stage (bad device vs. good device) without the feedback loops.

Of course, you need a working knowledge of how the stages work so you can excite them properly. The stage in the bad device that gives a different output as the good device will be your culprit. Zero in on the defect by further microprobing.

FARel Engr