Search found 21 matches

Guys,

Need some help...

We have SBGA packages more the 600 I/Os being tested. Usually an O/S failure which is considered Bin5 are caused either by wire shorting or lifted ball/stitch.

Lifted ...

Guys,

Any idea when this will be? Can an engineer working from a company not a member of ASEMEP join the symposium? A friend of mine wants to attend.

Thanks.

if we were given a dicied wafer which has went thru dicing process.(before mounting), how to judge whether the diced wafer is a good wafer or not??

The question is confusing. Do you mean if the qua ...

I'm a process engineer assigned at BE area. Could anybody help provide standard stand-off and coplanarity measurement procedure? I'm still new at TFS, so I think, i'll be needing a lot of tips from yo ...

Hello EE;

Our team is confused, we recently did a eutectic die attach (die back - 100 wt %) on one of our package using ESEC 2005HR @ 420ºC bond temp. We were able to get very good and stable die s ...

Hi,

Since UV is done after WM, i would assume you are using UV tape...

First, am not sure why you perform UV after WM. What is it for? Isn't UV exposure done prior DA to lessen the adhesion of t ...

Guys,

Just curious...

If I have two sets of samples coming from the same lot and subjected in the following conditions:

1. Precon/MRT and staged for a month inside N2 cabinet, then HAST.
2. ...

Ever felt that as an FA/Rel Engr you got typecast for this function that when you applied in another field such as process or product Engineering, you get ignored or rejected.

Not if you've been a ...

You can to do O2 plasma before marking..

I never knew you need to do plasma prior laser marking. I only know it is used on ink mark.

Is it good to have a 3rd optical inspection gate (after wirebond inpsection)? Or it is just a non-value added activity.

It really would depend on your objective.

I would go for 3opt elimination ...

Also, as a follow-up question on this topic (and out of curiosity), what is already the highest I/O count (if that's the proper term) for any package assembled here in the Philippines? Does anybod ...

Hello!

I just heard that TI is doing an 8 stacked-die with 560 (really fine pitched!) wires. Do any of you guys have any idea how these parts are packaged? Thanks!

Guys,

I think stack die tec ...

Are there leads on a flip chip or LGA? I think these are leadless.

LGAs I think are leadless. The "lands" replaced the leads. I believe this was patterned from CLCC (ceremic leadless chip carriers ...

What are the possible conditions that the Au die backside will not adhere properly to a die attach epoxy (specificaly Ablestik 84-1 material), i.e., failed die shear,etc.?
Another is, assuming it pa ...

I think FCBGA (Flip Chip Ball Grid Arrays) should be the package with highest I/Os...at least for now. A 27mm x 27 mm package could cater as much as 1500 to 2000 I/Os. This is packaged in a way that t ...