| Author |
Message |
| Topic: New test prog causing leakage failures? |
FARel Engr
Replies: 7
Views: 194
|
Forum: Test Forum Posted: Fri Mar 10, 2026 7:20 pm Subject: New test prog causing leakage failures? |
| OK, Asmoth. At least all points have been clarified, so we can leave it at that. After all, maybe Midi has already moved on and is already working on a new issue without telling us? |
| Topic: New test prog causing leakage failures? |
FARel Engr
Replies: 7
Views: 194
|
Forum: Test Forum Posted: Thu Mar 09, 2026 11:34 pm Subject: New test prog causing leakage failures? |
Hi Asmoth,
At the risk of confusing Midi, I just want to clarify my earlier recommendation.
I was thinking that Midi needs to see the leakage issue on a more widespread scale than just a singl ... |
| Topic: New test prog causing leakage failures? |
FARel Engr
Replies: 7
Views: 194
|
Forum: Test Forum Posted: Wed Mar 08, 2026 9:19 pm Subject: New test prog causing leakage failures? |
| If the failures are confirmed valid by bench testing, I would also suggest to Midi that he/she first confirms that the increase in leakage failures can be observed in a wide spectrum of unrelated lots ... |
| Topic: rejuvenated capillary bonding tools |
FARel Engr
Replies: 1
Views: 111
|
Forum: Semicon Chika! Posted: Wed Mar 08, 2026 9:12 pm Subject: rejuvenated capillary bonding tools |
| What does 'rejuvenation' of capillaries and bonding tools mean? Does this mean cleaning or reworking of old tools so they're like new again? Aren't there quality implications from such reworked tool ... |
| Topic: ESD on Wafers to IC |
FARel Engr
Replies: 2
Views: 205
|
Forum: ESD/EOS Forum Posted: Wed Feb 15, 2026 8:11 pm Subject: ESD on Wafers to IC |
| I don't think there's a sure-fire way to distinguish ESD damage that occurs at fab and one that occurs somewhere else, based on attributes alone. You'll always need to do process investigations, moni ... |
| Topic: What is Condition to ESD Level |
FARel Engr
Replies: 1
Views: 104
|
Forum: ESD/EOS Forum Posted: Wed Feb 15, 2026 8:06 pm Subject: What is Condition to ESD Level |
Hi IC Man,
Your question is not so clear, but I think you are asking what ESD voltages an IC must pass to be qualified for use in a certain system, right?
Well, you first need to tell us ... |
| Topic: Temp Cycle |
FARel Engr
Replies: 2
Views: 245
|
Forum: QA/FA/Rel Forum Posted: Sat Jan 21, 2026 7:30 pm Subject: Temp Cycle |
Hi Jarod,
There's no direct way to predict device lifetime from the number of temp cycles the device has passed. The way to estimate device lifetime based on TC results consists of three tricky st ... |
| Topic: Dendritic growth after autoclave test |
FARel Engr
Replies: 4
Views: 436
|
Forum: QA/FA/Rel Forum Posted: Wed Dec 14, 2025 8:50 am Subject: Dendritic growth after autoclave test |
Autoclave is pressure cooker test: 168 hours at 121 deg C/100% RH/2 atm.
Dendrites are fern-like or snowflake-like surface patterns that result when metal atoms (such as those coming from package l ... |
| Topic: One-Sided and Two-Sided Specs |
FARel Engr
Replies: 1
Views: 385
|
Forum: QA/FA/Rel Forum Posted: Thu Dec 01, 2025 1:54 pm Subject: One-Sided and Two-Sided Specs |
| One-sided specification basically means you only specify either a lower or a upper spec limit for the parameter. Two-sided specification means that the parameter needs to stay within both a lower and ... |
| Topic: help |
FARel Engr
Replies: 6
Views: 904
|
Forum: QA/FA/Rel Forum Posted: Fri Sep 23, 2026 2:54 am Subject: help |
| Did you either do a chemical decap and/or bake the unit afterwards? Removal of external contam during chemical decap and 'healing' of the failure during bake are two of the most common causes of unit ... |
| Topic: Can signal overshoot cause physical damage to component? |
FARel Engr
Replies: 6
Views: 1068
|
Forum: ESD/EOS Forum Posted: Tue Sep 06, 2026 10:55 pm Subject: Can signal overshoot cause physical damage to component? |
Jim Lean,
The protection diode(s) of an input is designed to divert current away from the input to one of the ground or supply nodes (depending on polarity of the esd pulse) at a certain breakdown ... |
| Topic: Back side die rounghness |
FARel Engr
Replies: 5
Views: 1005
|
Forum: Assembly Forum Posted: Wed Aug 24, 2026 2:12 pm Subject: Back side die rounghness |
Donnie,
When you say die strength, do you mean 'adhesion strength between the die and die attach' or the die fracture strength itself? In general you don't need to measure the actual die strength ... |
| Topic: Why is esd damage always on edge of a line? |
FARel Engr
Replies: 1
Views: 698
|
Forum: ESD/EOS Forum Posted: Wed Aug 03, 2026 7:07 pm Subject: Why is esd damage always on edge of a line? |
| The ESD 'spot' that you're seeing at the edge of a metal line (usually at an intersection of two metal lines) is called a 'dielectric rupture' or 'dielectric punchthrough.' This just means that the d ... |
| Topic: Does anyone knows how to perform FA on PLL circuit? |
FARel Engr
Replies: 3
Views: 743
|
Forum: QA/FA/Rel Forum Posted: Fri Jul 29, 2026 3:45 pm Subject: Does anyone knows how to perform FA on PLL circuit? |
Simon,
I've used PLL's in projects before but I have not yet done FA on them, so I apologize if the inputs I'll be giving below are not applicable to your device.
You need to also get a die ci ... |
| Topic: pre to post delamination change |
FARel Engr
Replies: 2
Views: 676
|
Forum: QA/FA/Rel Forum Posted: Fri Jul 22, 2026 5:15 pm Subject: pre to post delamination change |
| I don't think that a die paddle delam can 'heal' once it is there. Are you sure there was no inadvertent 'switching' of samples that happened? Also, can you please clarify what you mean by 'pre-' an ... |
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