Poor design of products will also lead to low test yields, manifesting as oversensitive devices that fail at the slightest hint of process or operational variation. However, not all circuit sensitivity issues may be attributed solely to improper product design. In some instances, limitations in the design technology itself simply can not compensate for parameter variability inherent to wafer fab processes. For instance, variations in substrate doping, ion implant dosage, and gate oxide thickness can affect the threshold voltage of MOS devices.

Even if the product is properly designed and no processing problems are encountered, a lot may also exhibit test yield issues as a result of the presence of point defects on the wafer.  Point defects are usually due to dust or particulate contamination in the environment or equipment issues where the wafer was processed.  Point defects may also be due to crystallographic imperfections within the silicon wafer itself.

Yield loss mechanisms must be understood in order to keep manufacturing costs in control, evaluate process capabilities better, and predict the performance of future products.  To understand yield loss mechanisms, these are mathematically expressed in terms of 'yield models', which are equations that translate defect density distributions into predicted yields. Examples of yield models used by IC manufacturers are the Poisson Model, the Murphy Model, the Exponential Model, and the Seeds Model.

Choosing a yield model is usually done based on the actual data being experienced by the IC manufacturer.  Yield  data from a specific fab process, for instance, may be analyzed per die size and compared to results predicted by the various models.  The model that provides a best fit for the data may be adopted for use in subsequent yield analyses.

One simple yield model assumes a uniform density of randomly occurring point defects as the cause of yield loss. If the wafer has a large number of chips (N) and a large number of randomly distributed defects (n), then the probability Pk that a given chip contains k defects may be approximated by Poisson's distribution, or Pk = e^-m (m^k/k!) where m = n/N.  The yield Y is the probability that a chip has no defects (k=0), so Y = e^-m.  If D is the chip defect density, then D = n/N/A = n/NA where A is the area of each chip.  Since m=n/N, then m, which is the average number of defects per chip, is AD. Thus, Y = e ^(-AD), which is the Poisson Yield Model.

Many experts believe that the Poisson Model is too pessimistic, since defects are often not randomly distributed, but rather clustered in certain areas.  Defect clustering allows less defects over large areas of the wafer than if the defects are randomly and uniformly distributed.

A simple model that assumes a non-uniform distribution of defects gives the yield Y as: Y= ₀∫^∞ e ^(-AD) f(D) dD, where f(D) is the distribution of the defect density.  Assuming a triangular defect density distribution as shown in Figure 1a, Y = [(1-e^(-AD))/(AD)]². This is Murphy's Yield Model.  For a rectangular defect density distribution as shown in Fig. 1b, Y = (1-e^(-2AD))/(2AD). Many experimental data fit this last equation, where the defect density is assumed to be rectangular.