System in a Package (SIP) : The 3-D Package

See Also:

System-on-a-Chip

Flip Chip Assembly

Chip Scale Package

Semicon Assembly

Semicon Manufacturing

System in a Package (SIP) - Page 2 of 2

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One challenge posed by die stacking is the need to keep the stack thermally and mechanically stable on the substrate, while allowing good interconnection among the die, and keeping the package as thin as possible in doing so. Needless to say, package thickness largely depends on the number of die that are vertically stacked inside. For instance, current technology would generally require a 1.4-mm chip scale package (CSP) to accommodate a six-die stack whereas a four-die stack can fit within a 1.2-mm CSP.

For more details about die stacking, please see the article: Die Stacking.

Flip chip bonding is also used in SIP interconnection, either on its own or as a complement to wirebonding. Flip chip configuration may be applied either to the upper die or the lower ones, depending on the intent of the design. Flip chipping a bottom die directly onto the substrate enables that die to operate at a high speed. On the other hand, flip chipping a top die eliminates the use of long wires for connection to the substrate.

Figure 2. Example of a 3-die SIP configuration employing

both wirebonding and flip chip bonding

Heat dissipation is another challenge in the development of SIP's. Taking chips off-the-shelf and using them in SIP's isn't always easy from the thermal point of view, since these chips were designed to dissipate heat through their own packages. Crowding them all together inside a SIP can accumulate enough heat to be of major concern in the field. Thermal management is therefore an important ingredient of any SIP development process.

SIP manufacturing not only offers assembly challenges, but test challenges as well. SIP's combine microelectromechanical systems, optoelectronic devices, various sensors, linear and digital circuits, etc., which were built on a different wafer fab process technologies and therefore have varying excitation requirements. Add to this the fact that each of these system blocks require special test methods of its own. A test solution to meet the various test resources and methods required by a complex SIP can turn out to be expensive.

For these test issues, some quarters propose a cost-effective solution in the form of an open-architecture automated test equipment (OA-ATE) that allows semiconductor manufacturers to specify their own test resource and instrumentation requirements. 'Specialization' of test capability nonetheless require some standardized vital elements: 1) an industry-standard bus structure; 2) compatibility with industry-standard data formats; 3) browser technology to access and control resources; 4) a modular hardware and software structure to enable reconfigurability; and 5) partitioned test supported by ATE and EDA tools.

Successful implementation of SIP manufacturing brings in many advantages that are important to the semiconductor industry of the future: shorter time-to-market, lower cost, flexibility, smaller size, etc. To get there, however, requires a monumental engineering effort to address all technical obstacles along the way.

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