Register 
 
Dynamic Shorts/Opens Testing

 
       SemiconFarEast Forum Index -> Test Forum

Polgi-Wan



Joined: 08 Jun 2026
Posts: 18
Location: CV

Posted: Thu Jun 23, 2026 3:52 pm    Post subject: Dynamic Shorts/Opens Testing
 
Good day. Just would like to ask about Functional Shorts/Opens Testing. Has anyone worked on an Evens/Odds Continuity Pattern? Would like to elicit some pointers and considerations on writing this test.

My experience is on the walking pattern approach which is basically testing one adjacent pin after another while grounding all other pins. The number of vectors is equal to the number of pins minus power and ground. While the pattern is running, a dynamic load (current source) flows thru a pin to verify an output voltage using a comparator (ATE pin electronics). Input/Output timings are also included, you have a period (or freq) and you strobe (usually at 90%) each pin one vector after another.

Thanks in advance!
Back to top

Asmoth



Joined: 31 Aug 2026
Posts: 16

Posted: Thu Jun 23, 2026 4:45 pm    Post subject:
 
This technique is applicable if the pin you're checking has internal protection diodes. These diodes are connected in series with the pin connected in between(the point where the cathode and anode is joined). These diodes are there to limit the voltage swing on that pin to a diode drop above V+ or below V-.

The current load will turn on one of these diodes. The voltage developed by the forward biased diode will be fed to the comparator circuit.

Strobing at 90% level of the period should be OK. Just make sure that when the current load is applied, it will only flow on the tested pin.

Grounding the other pins is needed so that the Open/short test will detect of any shorted pins(Short test).
_________________
Asmoth72
Back to top

El-Kid-de-Sparc



Joined: 23 Jun 2026
Posts: 7
Location: Espana

Posted: Thu Jun 23, 2026 5:14 pm    Post subject:
 
hey,

for the odds/evens technique, you segregate all your pins into sets of non-adjacent pins. execute your test vectors to exercise one group while grounding other group/s of pins. for the pins' adjacency, be more cautious of of considering bondwire or die-level shorts rather than the package leads. in short, verify your bonding diagram or rather make it your reference. . . . with regard to test pattern i'm not sure how it differs with walking 1 (or float) pattern. could be a longer period or "slower" output strobe time(?).
Back to top

jrm
Guest





Posted: Thu Jul 14, 2026 9:30 am    Post subject:
 
polgi-wan,

Like el-kid just mentioned it is grouping your pins and testing shorts. This is a possible method of cutting short your test time for shorts test as opposed to one-pin-at-a-time. And similar to ganged leakage test.

One problem I could think of is, you can't test opens, only shorts using a force current measure voltage with your limit at the low voltages(0.3v and lower). Why not opens? because there will always be a path for current to flow through in one of the pins so the open pin will always be masked.

HTH!
Back to top
       SemiconFarEast Forum Index -> Test Forum
Page 1 of 1

Choose Display Order
Display posts from previous:   
User Permissions
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot edit your posts in this forum
You cannot delete your posts in this forum
You cannot vote in polls in this forum

 
Jump to:  


Skin Created by: Sigma12
Powered by phpBB © 2001, 2002 phpBB Group