Si die cracking

rel gal · Guest

Hi,
Can cracks in the Si die result in low resistance measurements between the Si substrate and each of the I/O pins? If so, what would be the explanation?

Thanks

testeng99 · Joined: 20 Jun 2026 Posts: 17

Hi rel gal,

Yup, if you're just asking if it's possible. I once asked this question to our FA engr. He said that gross die cracking can shift circuit features with respect to each other, so features that are previously isolated may become 'shorted' after gross die cracking. Same is true for open circuits. Why don't you ask your FA too?

Test Engg 99

rel gal · Guest

Thanks, test eng. 99.
Well, I AM the FA person and our buisiness is CSP packaging so when it comes to isolating IC failures- we're kinda learning as we go along.
But, going back to the subject- what do you mean by "gross cracking" is a few microns (say up to 20 microns of a branching crack)- would this go under "gross"? BTW, we do CSP packaging so with respect to the final Si die which is about 130 microns thick- how would a 20 microns crack pass?
In the past we DID encounter a very wide traversing crack that went through the width of the die (due to a processing problem) and indeed the customer reported back major problems with high current measurements- so I guess this backs up the early supposition.

FARel Engr · Joined: 20 Jun 2026 Posts: 43

Hi Rel Gal, Test Engg 99,

I jst want to give my opinion on this. The elec. failure mode can not be correlated with the 'size' of the crack. It should instead be correlated with 'how' the crack propagation caused the device to exhibit the low R readings. You therefore need to do a few FA steps to determine what really happened.

1) Curve Trace Results: Which pin exhibits the worst reading wrt the substrate? Is the substrate connected to any pin (say, ground)? What is the worst reading? Is it almost a short (a few hundred ohms)?

2) Hot Spot Detection: If you see a resistive short, do the liquid crystal technique while exciting the worst pins of the device with a curve tracer. You should see a hot spot that tells you where the current is going. Just be aware that not everything that heats up is the defective part, so be careful with your conclusion.

3) Visual Inspection: Check if the hot spot is in any way connected with the crack. Do high-power inspection to see if you can relate the location of the hot spot to the crack damage.

4) Probing: Probe the hot spot area to determine where the current is really going. Again, try to relate your findings with how the crack propagated.

Without these FA steps it would be really difficult to know how your cracking is related to your electrical failure mode. BTW, if you see a die crack in all your failures, then it is often safe enough to conclude that the elec. failures are indeed due to the die cracks, so you should instead use your resources finding the cause of the cracks. How many returns did you get? Are all of them due to die crack?

Hope this helps. Good luck and keep us posted!

FARel Engr

rel gal · Guest

Hi FAREL eng,
Thank you so much for your learned and detailed response.
Like I said, we're a packaging FAB and do not have the apparatus nor the knowledge to perform the tests that you suggested. When a CONTINUITY issue arrises we rely on very few invetigative steps to help build an understanding of the failure:
(1) The customer's response once he performs the detailed electrical test (I suppose some of the steps are what you indicated)
(2) Communality across the wafer (i.e., preferred failure location etc.)
(3) A few Cross sections of the packaged die to see if the exact failed pin correspondes with abnormal cross sectional findings.

So far, the latter two steps are checked so now we expect to see if the customer verifies and how he correlates with our findings.
BTW, the low resistivity results are indeed all related to the ground which is the Si substrate. Also, they are always consequtive pins and in the same dicing channel.

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