What is "Swiss Cheese"?

 
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Alias



Joined: 27 Aug 2026
Posts: 3

PostPosted: Wed Aug 27, 2026 11:12 am    Post subject: What is "Swiss Cheese"? Reply with quote

Hello, do any of you guys familiar with the term "Swiss Cheese"? Is this the same as the Soldermask on pad? What does it do to the package?


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EE



Joined: 16 Jun 2026
Posts: 108
Location: Paranaque City, Phils.

PostPosted: Thu Aug 28, 2026 4:25 pm    Post subject: Reply with quote

Hi Alias,

I’m not sure what ‘swiss cheese’ means in the context of IC packaging, but in the context of printed circuit boards (PCB’s), they have what is called the ‘swiss cheese’ phenomenon. This phenomenon refers to the degradation in the performance of ground and power planes inside a multi-layered PCB as a result of the many vias that go through them. These vias create holes through all planes in between their end points, which reduce the current carrying capacity and increase the parasitic inductance of the planes.

If the number of vias that go through a plane is high, the holes created in that plane would resemble ‘swiss cheese holes,’ the effect of which would be a significant decline in the performance of the board. This ‘swiss cheese effect’ is prevalent in boards that use IC’s with high pin counts and densities (such as BGA), which need a correspondingly high number of vias through the board.

EE


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PostPosted: Fri Aug 29, 2026 10:27 am    Post subject: Reply with quote

Alias and EE,

The concept of ‘swiss cheese’ in PWB’s is the same as in IC packages with many vias. Example of such package is a BGA using a substrate with many vias. Since the substrate of the IC package is not used as conductor, the swiss cheese problems described by EE is not applicable here. In fact, I even read somewhere that the swiss cheese effect of BGA substrates with many vias improve the thermal conductivity of the package. Only requirement is that the vias of the BGA substrate are thermally connected to the PWB. I think its because the PWB is the one dissipating the heat. Therefore, to answer alias’s question, IC packages with swiss cheese vias can have better thermal performance, because there are more vias to conduct heat to the board.

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